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Fix some typos

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This commit is contained in:
Kovid Goyal
2024-02-01 21:25:37 +05:30
parent 2549b4328f
commit 601c4ad4df
3 changed files with 13 additions and 8 deletions
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15
tools/simdstring/generate.go
View File

@@ -324,7 +324,7 @@ func (f *Function) set_return_value(offset int, q FunctionParam, val any) {
if f.ISA.Goarch == ARM64 && strings.HasPrefix(vr, `$`) { if f.ISA.Goarch == ARM64 && strings.HasPrefix(vr, `$`) {
// no way to store an immediate value into a memory address // no way to store an immediate value into a memory address
temp := f.Reg() temp := f.Reg()
f.SetRegsiterTo(temp, val) f.SetRegisterTo(temp, val)
defer f.ReleaseReg(temp) defer f.ReleaseReg(temp)
vr = temp.Name vr = temp.Name
} }
@@ -590,7 +590,7 @@ func (f *Function) And(a, b, dest Register) {
f.instr("PAND", a, dest) f.instr("PAND", a, dest)
} }
} else { } else {
f.instr("VAND", a, b, dest) f.instr("VPAND", a, b, dest)
} }
} }
f.AddTrailingComment(dest, "=", a, "&", b, "(bitwise)") f.AddTrailingComment(dest, "=", a, "&", b, "(bitwise)")
@@ -663,7 +663,7 @@ func (f *Function) CopyRegister(a, ans Register) {
f.AddTrailingComment(ans, "=", a) f.AddTrailingComment(ans, "=", a)
} }
func (f *Function) SetRegsiterTo(self Register, val any) { func (f *Function) SetRegisterTo(self Register, val any) {
switch v := val.(type) { switch v := val.(type) {
case Register: case Register:
f.CopyRegister(self, v) f.CopyRegister(self, v)
@@ -680,7 +680,7 @@ func (f *Function) SetRegsiterTo(self Register, val any) {
if f.ISA.Goarch == ARM64 { if f.ISA.Goarch == ARM64 {
f.instr("MOVD", val_repr_for_arithmetic(v), self) f.instr("MOVD", val_repr_for_arithmetic(v), self)
} else { } else {
f.instr(f.MemLoadForBasicType(types.Int32), val_repr_for_arithmetic(v), self) f.instr("MOVL", val_repr_for_arithmetic(v), self)
} }
f.AddTrailingComment(self, "= ", v) f.AddTrailingComment(self, "= ", v)
} }
@@ -770,7 +770,8 @@ func (f *Function) Set1Epi8(val any, vec Register) {
f.Comment("Set all bytes of", vec, "to", v) f.Comment("Set all bytes of", vec, "to", v)
r := f.Reg() r := f.Reg()
defer f.ReleaseReg(r) defer f.ReleaseReg(r)
f.SetRegsiterTo(r, v) f.SetRegisterTo(r, v)
if f.ISA.Goarch == ARM64 { if f.ISA.Goarch == ARM64 {
f.instr("VMOV", r, vec.ARMFullWidth()) f.instr("VMOV", r, vec.ARMFullWidth())
} else { } else {
@@ -812,8 +813,8 @@ func (f *Function) Set1Epi8(val any, vec Register) {
switch vec.Size { switch vec.Size {
case 128: case 128:
r := f.LoadParam(v) r := f.LoadParam(v)
do_shuffle_load(r)
defer f.ReleaseReg(r) defer f.ReleaseReg(r)
do_shuffle_load(r)
case 256: case 256:
f.instr("VPBROADCASTB", f.ParamPos(v), vec) f.instr("VPBROADCASTB", f.ParamPos(v), vec)
} }
@@ -1021,7 +1022,7 @@ func (f *Function) SubtractFromSelf(self Register, val any) {
func (s *Function) SetRegisterToOffset(dest Register, base_register Register, constant_offset int, offset_register Register) { func (s *Function) SetRegisterToOffset(dest Register, base_register Register, constant_offset int, offset_register Register) {
if s.ISA.Goarch == ARM64 { if s.ISA.Goarch == ARM64 {
s.SetRegsiterTo(dest, constant_offset) s.SetRegisterTo(dest, constant_offset)
s.AddToSelf(dest, base_register) s.AddToSelf(dest, base_register)
s.AddToSelf(dest, offset_register) s.AddToSelf(dest, offset_register)
} else { } else {

4
tools/simdstring/intrinsics.go
View File

@@ -39,6 +39,8 @@ func get_safe_slice_with_cap(addr uintptr, mask, datalen, datacap int) (align_le
return get_safe_slice(addr, mask, datalen) return get_safe_slice(addr, mask, datalen)
} }
// Return the index at which either a or b first occurs in data. If neither is
// found -1 is returned.
func IndexByte2(data []byte, a, b byte) int { func IndexByte2(data []byte, a, b byte) int {
align_len, vecsafe_len := get_safe_slice_with_cap(uintptr(unsafe.Pointer(&data)), VectorSize-1, len(data), cap(data)) align_len, vecsafe_len := get_safe_slice_with_cap(uintptr(unsafe.Pointer(&data)), VectorSize-1, len(data), cap(data))
if align_len > 0 { if align_len > 0 {
@@ -61,6 +63,8 @@ func IndexByte2(data []byte, a, b byte) int {
return -1 return -1
} }
// Return the index at which either a or b first occurs in data. If neither is
// found -1 is returned.
func IndexByte2String(data string, a, b byte) int { func IndexByte2String(data string, a, b byte) int {
align_len, vecsafe_len := get_safe_slice(uintptr(unsafe.Pointer(&data)), VectorSize-1, len(data)) align_len, vecsafe_len := get_safe_slice(uintptr(unsafe.Pointer(&data)), VectorSize-1, len(data))
if align_len > 0 { if align_len > 0 {

2
tools/simdstring/intrinsics_test.go
View File

@@ -200,7 +200,7 @@ func TestSIMDStringOps(t *testing.T) {
} }
c0tests("") c0tests("")
c0tests("a") c0tests("abcdef")
c0tests("a\x00") c0tests("a\x00")
c0tests("afsgdfg\x7f") c0tests("afsgdfg\x7f")
c0tests("a\nfgdfgd\r") c0tests("a\nfgdfgd\r")